839 Commits
Author SHA1 Message Date
Sebastian Macke 9577065978 Update 2019-05-20 23:08:46 +02:00
Sebastian Macke d09a15ac96 Do not set forbidden Content-Length parameter and fix potential mtime problem 2019-05-20 23:08:20 +02:00
Sebastian Macke 1c0480c07f Riscv: Add new floating point instruction 2019-05-20 22:23:44 +02:00
Sebastian Macke 90b38c4091 Update 2019-05-06 21:13:11 +02:00
Sebastian Macke 67e7cf037d Update 2019-05-06 21:11:58 +02:00
Sebastian Macke b46f9e058e RISCV: Add fast tlb lookup 2019-04-29 00:01:16 +02:00
Sebastian Macke 3c20e12476 RISCV: Direct RAM access 2019-04-28 22:14:47 +02:00
Sebastian Macke 25ad8f88e4 Add stacktrace output on error 2019-04-28 18:08:22 +02:00
Sebastian Macke c88dbcd619 Fix riscv webassembly support 2019-04-28 18:08:05 +02:00
Sebastian Macke 3ab26f2f2b Switch to clang compiler for webassembly. Initial code for webassembly RISCV-cpu 2019-04-26 22:56:58 +02:00
Sebastian Macke e184f62a32 Update package.json 2019-04-06 09:58:48 +02:00
Sebastian Macke 5075e059c0 Add webassembly cpu core 2019-04-06 09:57:57 +02:00
Sebastian Macke 0d0d451e85 Update 2018-06-01 22:08:33 +02:00
Sebastian Macke 7c6161309c Add new instructions to smp and dynamic CPU 2018-06-01 22:08:14 +02:00
Sebastian Macke ae4684410e Update 2018-06-01 14:29:50 +02:00
Sebastian Macke b04772a716 Fix divide instruction 2018-05-21 14:49:04 +02:00
Sebastian Macke 27d9ac4690 Remove broken scrollbuffer from terminal 2018-05-21 00:58:21 +02:00
Sebastian Macke 4ce67547c8 Update 2018-05-21 00:24:41 +02:00
Sebastian Macke 3c86280809 New instruction support. Support for carry flag and several bugfixes 2018-05-21 00:20:14 +02:00
Sebastian Macke 454784af39 Count links in directory 2017-11-08 21:43:15 +01:00
Sebastian Macke 4f8f5b6ef6 Update README.md 2017-11-02 19:49:30 +01:00
Sebastian Macke a24d02c504 Remove core switch functionality 2017-06-04 18:13:57 +02:00
Sebastian Macke 961316910e Change time step cycles from 64 to 1024 2017-06-04 17:56:19 +02:00
Sebastian Macke e07dbe1e72 UART: Fix fifo clear and clean up 2017-06-04 17:29:12 +02:00
Sebastian Macke db367a6cc3 Update 2017-05-28 23:40:47 +02:00
Sebastian Macke 5b62ae8c0b Dynamic CPU: Use working path 2017-05-28 23:34:20 +02:00
Sebastian Macke afe36506f6 New message to retrieve the path variable 2017-05-28 22:26:14 +02:00
Sebastian Macke 4bc0b8270f New upper limit for timer 2017-05-28 21:26:10 +02:00
Sebastian Macke 904fa23203 Reactive dynamic core 2017-05-28 21:25:38 +02:00
Sebastian Macke 6249c4d878 Update 2017-05-13 21:24:31 +02:00
Sebastian Macke 9b25451be9 Trap misaligned load and store and check for compressed instructions 2017-05-13 21:20:44 +02:00
Sebastian Macke 1367feaaf5 Update 2017-05-10 19:43:12 +02:00
Sebastian Macke 0ab0136c6b Add idle state for RISCV and correct the delta time calculation of the other CPUs 2017-05-10 19:42:53 +02:00
Sebastian Macke 653bdd7608 Update 2017-05-09 22:58:04 +02:00
Sebastian Macke 131ae4f784 RISCV: Update timer handling. Default is not 20 Mhz 2017-05-09 22:53:30 +02:00
Sebastian Macke 6da3827478 Add extended fs to riscv emulation and add div instruction 2017-05-07 21:59:59 +02:00
Sebastian Macke e9bd096dd5 Update riscv-sys 2017-05-07 20:20:38 +02:00
Sebastian Macke 715ba25f2e Update riscv-sys 2017-05-07 20:14:51 +02:00
Sebastian Macke 2836863f80 Fix RISCV paths 2017-05-07 18:30:11 +02:00
Sebastian Macke f9b7d714aa Remove unused dynamic cpu 2017-05-07 17:47:01 +02:00
Sebastian Macke cce30da8b1 Compile 2017-05-07 17:39:58 +02:00
Sebastian Macke 0c7c4b4646 Consistent folder structure and small fixes on the websites 2017-05-07 17:38:06 +02:00
Sebastian Macke 5835e7a0c7 rename submodule 2017-05-07 16:02:04 +02:00
Sebastian Macke 360fa4255e Add submodule 2017-05-07 15:19:06 +02:00
Sebastian Macke bff61a8f69 Merge branch 'riscv-new-priv' 2017-05-07 15:10:18 +02:00
Sebastian Macke 330ff1ec7e Fix folders 2017-05-07 15:06:55 +02:00
Sebastian Macke 5ac06876f5 Merge pull request #129 from LARPY/dev
Added the ability to select the upload/download path
2017-05-07 14:41:02 +02:00
Sebastian Macke 0cb97f12ce Merge pull request #127 from mrabault/inode_timestamps
Fix bug #125
2017-05-07 14:35:34 +02:00
Sebastian Macke b85a79694d Several improvements for RISCV CPU 2017-05-07 14:28:57 +02:00
Sebastian Macke f05ea46587 Fix debug output 2017-05-07 12:20:16 +02:00